1. Field of the Invention
This invention relates to a semiconductor memory device of the random access type, which performs independent read and write operations through a plurality of ports.
2. Description of the Related Art
A semiconductor memory device of the random access type in which the read and write operations are independently performed through two ports, has been known as a 2-port RAM. A portion including a single memory cell in the 2-port RAM is schematically illustrated in FIG. 1. A pair of inverters connected in a back-to-back fashion make up flip-flop (F/F) 11 retaining one-bit complementary data. Transfer gates 12 and 13 are coupled at node N1 retaining one of the complementary data. Transfer gates 14 and 15 interconnect at node N2 retaining the other of the complementary data. Two pairs of bit lines BL0 and BL0, and BL1 and BL1 are provided. Transfer gate 12 is connected between bit line BL0 and node N1. Similarly, transfer gate 13 is connected between bit line BL1 and node N1. Transfer gate 14 is connected between bit line BL0 and node N2. Transfer gate 15 is connected between bit line BL1 and node N2. The gates of transfer gates 12 and 14 are connected together to word line WL0; the gates of transfer gates 13 and 15 are connected together to word line WL1.
In the above memory cell, when word line WL0 is driven, transfer gates 12 and 14 are conductive, and nodes N1 and N2 of F/F 11 are coupled with bit lines BL0 and BL0, respectively. At this time, the data retained in F/F 11 is read out onto bit line pair BL0 and BL0, or data supplied onto this bit line pair is written into F/F 11. When word line WL1 is driven, transfer gates 13 and 14 are conductive, and nodes N1 and N2 of F/F 11 are coupled with bit lines BL1 and BL1, respectively. At this time, the data retained in F/F 11 is read out onto bit line pair BL1 and BL1, or data supplied on this bit line pair is written into F/F 11.
Combinations of read and write operations possibly performed for the 2-port RAM including a number of such memory cells arrayed in a matrix fashion are as shown in FIG. 2. The operation modes of the RAM may be categorized into three types: mode 1 in which neither port 0 or port 1 is selected; modes 2, 3, 7, 8 in which either port 0 or port 1 is selected; modes 4, 5 and 6 in which both port 0 and port 1 are selected. Port 0 indicates a terminal connecting to bit line pair BL0 and BL0 through which data is written to and read out of the memory cell. Port 1 indicates a terminal connected to bit line pair BL1 and BL1 through which data is written to and read out of the memory cell. In each operation mode, when one port is selected, one of the bit line pairs BL0, BL0 and BL1, BL1 serves as a load, and no problem arises. When word lines WL0 and WL1 connected to memory cells in a row are both driven, and two ports are simultaneously selected, both the bit line pairs BL0, BL0 and BL1, BL1 serve as a load of F/F 11, and a problem arises. The problem follows. Before the read or write operation, bit line pairs BL0, BL0 and BL1, BL1 are precharged to "H" level by a precharge means (not shown). Subsequently, either of word lines WL0 and WL1 is driven, so that a pair of transfer gates connected to nodes N1 and N2, for example, transfer gates 12 and 14, are conductive, so that nodes N1 and N2 are connected to bit lines BL0 and BL0, respectively. Let us consider a read operation of the memory device. It is assumed that when F/F 11 stores such data that "H" level is at node N1 and "L" level at node N2, transfer gates 12 and 14 are conductive, and the nodes are connected to bit lines BL0 and BL0. After the nodes are connected to bit lines BL0 and BL0, potential on bit line BL0 changes from "H" to "L". In a circuit design, the drive ability of the inverters of F/F 11, for example, is selected on the assumption that such a potential change in bit lines is performed at a predetermined rate, with the bit lines respectively connecting to nodes N1 and N2. In a situation when two ports are selected and two bit lines are connected to nodes N1 and N2, two bit lines in "H" level must be discharged at the node set in "L" level in F/F 11. A rate of potential change in both the bit lines from "H" to "L" is lower than that in a single line. In such a situation, when a load varies, the read characteristic of the memory device, and the write characteristic as well varies.